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quad, 16 - /14 - /12 - bit nano dac+ with 2 ppm/c reference, spi interface data sheet ad5686r / ad5685r / AD5684R rev. b document feedback information furnished by analog devices is believed to be accurate and reli able. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implica tion or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features high relative accuracy (inl): 2 lsb maximum @ 16 bits low drift 2.5 v reference: 2 ppm/c typical tiny package: 3 mm 3 mm , 16 - lead lfcsp total unadjusted error (tue): 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1 % of fsr maximum high drive capability: 20 ma, 0.5 v from supply rails user selectable gain of 1 or 2 (gain pin) reset to zero scale or midscale (rstsel pin) 1.8 v logic compatibility 50 mhz spi with readback or daisy chain low g litch: 0.5 nv - s ec robust 4 kv hbm and 1.5 kv ficdm esd rating low power: 3.3 mw at 3 v 2.7 v to 5.5 v power supply ? 40c to +105c temperature range applications optical transceivers base - station power amplifiers process control (plc i/o cards) industrial a utomation data acquisition systems functional block dia gram figure 1. general description the ad5686r / ad5685r / AD5684R , members of the nano dac + ? family, are low power, quad, 16 - /14 - /1 2 - bit buffered voltage out put dacs. the devices include a 2.5 v, 2 ppm/ c internal reference (enabled by default) and a gain select pin giving a full - scale output of 2.5 v ( gain = 1) or 5 v ( gain = 2). all devices oper ate from a single 2.7 v to 5.5 v supply, are guaranteed monotonic by design , and exhibit less than 0.1% fsr gain error and 1.5 mv offset error performance . the devices are available in a 3 mm 3 mm lfcsp and a tssop package. the ad5686r / ad5685r / AD5684R also incorporate a power - on r eset circuit and a rstsel pin that ensures that the dac output s power up to zero scale or midscale and remain s there until a valid write takes place. each part contain s a per - channel power - down featur e that reduces the current consumption of the device to 4 a at 3 v while in power - down mod e. the a d5686r / ad5685r / AD5684R employ a versatile spi interface that operates at clock rates up to 50 mhz , and all devices contain a v logic pin intended for 1.8 v/3 v/5 v l ogic . table 1 . quad nano dac+ devices interface reference 16 - bit 14 - bit 12 - bit spi internal ad5686r ad5685r AD5684R external ad5686 ad5684 i 2 c internal ad5696r ad5695r ad5694r external ad5696 ad5694 product highlights 1. high relative accuracy (inl) . ad5686r (16 - bit): 2 lsb maximum ad5685r (14 - bit): 1 lsb maximum AD5684R (12 - bit): 1 lsb ma ximum 2. low drift 2.5 v on - chip reference . 2 ppm/ c typical temperature coefficient 5 ppm/ c maximum temperature coefficient 3. two package options . 3 mm 3 mm, 16 - lead lfcsp 16- lead tssop sclk v logic sync sdin sdo input register dac register string dac a buffer v out a input register dac register string dac b buffer v out b input register dac register string dac c buffer v out c input register dac register string dac d buffer v out d v ref gnd v dd 2.5v reference power- down logic power-on reset gain 1/2 interface logic rstsel gain ldac reset ad5686r/ad5685r/AD5684R 10485-001
ad5686r/ad5685r/AD5684R data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 gene ral description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteris tics ........................................................................ 5 timing characteristics ................................................................ 6 daisy - c hain and readback timing characteristics ................ 7 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 terminology .................................................................................... 18 theory of operation ...................................................................... 2 0 digital - to - analog converter .................................................... 20 transfer function ....................................................................... 20 dac archit ecture ....................................................................... 20 serial interface ............................................................................ 21 standalone operation ................................................................ 22 write and update commands .................................................. 22 da isy - chain operation ............................................................. 23 readback operation .................................................................. 23 power - down operation ............................................................ 24 load dac (hardware ldac pin) ........................................... 25 ldac mask register ................................................................. 25 hardware reset ( reset ) .......................................................... 26 reset select pin (rstsel) ........................................................ 26 internal reference setup ........................................................... 26 sold er heat reflow ..................................................................... 26 long - term temperature drift ................................................. 26 thermal hysteresis .................................................................... 27 applicatio ns information .............................................................. 28 microprocessor interfacing ....................................................... 28 ad5686r/ad5685r/AD5684R to adsp - bf531 interface .. 28 ad5686r/ad5685r/AD5684R to sport interface ............ 28 layout guidelines ....................................................................... 28 galvanically isolated interface ................................................. 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 31 revisio n history 6 / 13 rev. a to rev. b changes to pin gain and pin rstsel descriptions; table 6 ... 1 0 9 / 12 rev. 0 to rev. a changes to table 1 ............................................................................ 1 changes to figure 13 ...................................................................... 1 1 changes to figure 36 ...................................................................... 1 5 4 / 12 revision 0: initial version
data sheet ad5686r/ad5685r/AD5684R rev. b | page 3 of 32 specifications v dd = 2.7 v to 5.5 v; 1.8 v v logic 5.5 v ; a ll specifications t min to t max , unless otherwise noted. r l = 2 k?; c l = 200 p f. table 2 . a grade 1 b grade 1 parameter min typ max min typ max unit test conditions/comments static performance 2 ad5686r resolution 16 16 bits relative accuracy 2 8 1 2 lsb gain = 2 2 8 1 3 gain = 1 differential nonlinearity 1 1 lsb guaranteed monotonic by design ad5685r resolution 14 14 bits relative accuracy 0.5 4 0.5 1 lsb differential nonlinearity 1 1 lsb guaranteed monotonic by design AD5684R resolution 12 12 bits relative accuracy 0.12 2 0.12 1 lsb differential nonlinearity 1 1 lsb guaranteed monotonic by design zero - code error 0. 4 4 0. 4 1.5 mv al l zero s loaded to dac register offset error + 0. 1 4 + 0. 1 1.5 mv full - scale error + 0.0 1 0.2 + 0.0 1 0.1 % of fsr all ones loaded to dac register gain error 0.02 0.2 0.02 0.1 % of fsr total unadjusted error 0.01 0.25 0.01 0.1 % of fsr external reference; g ain = 2; tssop 0.25 0.2 % of fsr internal reference ; g ain = 1; tssop offset error drift 3 1 1 v/c gain temperature coefficient 3 1 1 ppm of fsr/c dc power supply rejection ratio 3 0.15 0.15 mv/v dac code = midscale; v dd = 5 v 10 % dc crosstalk 3 2 2 v due to single channel, full - scale output change 3 3 v/ma due to load current change 2 2 v due to powering down (per chan nel) output characteristics 3 output voltage range 0 v ref 0 v ref v gain = 1 0 2 v ref 0 2 v ref v gain = 2 , see figure 34 capacitive load stability 2 2 nf r l = 10 10 nf r l = 1 k ? resistive load 4 1 1 k ? load regulation 80 80 v/ma 5 v 10%, dac code = midscale; ? 30 ma i out 30 ma 80 80 v/ma 3 v 10%, dac code = midscale; ? 20 ma i out 20 ma short - circuit current 5 40 40 ma load impedance at rails 6 25 25 ? see figure 34 power - up time 2.5 2.5 s coming out of power - down mode; v dd = 5 v
ad5686r/ad5685r/AD5684R data sheet rev. b | page 4 of 32 a grade 1 b grade 1 parameter min typ max min typ max unit test conditions/comments reference output output voltage 7 2.4975 2.5025 2.4975 2.5025 v at ambient reference tc 8 , 9 5 2 0 2 5 ppm/c see the terminology section output impedance 3 0. 0 4 0. 0 4 ? output voltage noise 3 12 12 v p - p 0.1 hz to 10 hz output voltage noise density 3 240 240 nv/hz at ambient; f = 10 khz, c l = 10 n f load regulation sourcing 3 20 20 v/ma at ambient load regulation sinking 3 40 40 v/ma at ambient output current load capability 3 5 5 ma v dd 3 v line regulation 3 1 0 0 1 0 0 v/v at ambient long - term stability / drift 3 12 12 ppm after 1000 hours at 125c thermal hysteresis 3 125 125 ppm first cycle 25 25 ppm additional cycles logic inputs 3 input current 2 2 a per pin v inl , input low voltage 0.3 v logic 0.3 v logic v v inh , input high voltage 0.7 v logic 0.7 v logic v pin capacitance 2 2 pf logic output s (sdo) 3 output low voltage, v ol 0.4 0.4 v i sink = 200 a output high voltage, v oh v logic ? 0.4 v logic ? 0.4 v i source = 200 a floating state output capacitance 4 4 pf power requirements v logic 1.8 5.5 1.8 5.5 v i logic 3 3 a v dd 2.7 5.5 2.7 5.5 v gain = 1 v dd v ref + 1.5 5.5 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 10 0.59 0. 7 0. 5 9 0.7 ma internal reference off 1.1 1.3 1.1 1.3 ma internal reference on, at full scale all power - down modes 11 1 4 1 4 a ? 40c to +85c 6 6 a ? 40c to +105c 1 temperature range: a and b grade: ?40c to +105c. 2 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1 or when v ref /2 = v dd with gain = 2. linearity calculated using a reduced code range of 256 to 65 , 280 ( ad5686r ), 64 to 16 , 320 ( ad5685r ) , and 12 to 4080 ( AD5684R ) . 3 guaranteed by design and characterization ; not production tested. 4 channel a and channel b can have a combined output current of up to 30 ma. similarly, channel c and channel d can have a comb ined output current of up to 30 ma up to a junction temperature of 110c. 5 v dd = 5 v . the device includes current limiti ng that is intended to protect the device during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the specified max imum operation junction temperature may impair device reliability. 6 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 typical channel res istance of the output devices. for example , when sinking 1 m a, the minimum output voltage = 25 ? 1 ma = 25 mv ( see figure 34) . 7 initial accuracy presolder reflow is 750 v; o utput voltage includes the effects of preconditioning drift. see the i nternal refere nce setup section. 8 reference is trimmed and tested at two temperatures and is characteri z ed from ? 40c to +105c . 9 reference temperature coefficient calculated as per the box method. see the terminology section for further information. 10 interface inactive. all dacs active. dac out puts unloaded. 11 all dacs powered down.
data sheet ad5686r/ad5685r/AD5684R rev. b | page 5 of 32 ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; 1.8 v v logic 5.5 v ; all specifications t min to t max , unless otherwise noted. 1 table 3 . parameter 2 min typ max unit test conditions/comments 3 output voltage settling time ad5686r 5 8 s ? to ? scale settling to 2 lsb ad5685r 5 8 s ? to ? scale settling to 2 lsb AD5684R 5 7 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital -to - analog glitch impulse 0. 5 nv - sec 1 lsb change around major carry digital feedthrough 0.1 3 nv - sec digital crosstalk 0.1 nv - sec analog crosstalk 0.2 nv - sec dac -to - dac crosstalk 0.3 nv - s ec total harmonic distortion 4 ? 80 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density 300 nv/ hz dac code = midscale, 10 khz ; gain = 2 output noise 6 v p -p 0.1 hz to 10 hz snr 90 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz sfdr 83 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz sinad 80 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz 1 guaranteed by design and characterization, not production tested. 2 see the terminology section. 3 temperature range is ?40 c to +105c, typical @ 25c. 4 digitally generated sine wave @ 1 khz.
ad5686r/ad5685r/AD5684R data sheet rev. b | page 6 of 32 timing characteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 2. v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v; v refin = 2.5 v. all specifications t min to t max , unless otherwise noted. table 4. 1.8 v ? v logic < ? 2.7? v 2.7 v ? v logic ? 5.5? v parameter 1 symbol min max min max unit sclk cycle time t 1 33 20 ns sclk high time t 2 16 10 ns sclk low time t 3 16 10 ns sync to sclk falling edge setup time t 4 15 10 ns data setup time t 5 5 5 ns data hold time t 6 5 5 ns sclk falling edge to sync rising edge t 7 15 10 ns minimum sync high time (single, combined or all channel update) t 8 20 20 ns sync falling edge to sclk fall ignore t 9 16 10 ns ldac pulse width low t 10 25 15 ns sclk falling edge to ldac rising edge t 11 30 20 ns sclk falling edge to ldac falling edge t 12 20 20 ns reset minimum pulse width low t 13 30 30 ns reset pulse activation time t 14 30 30 ns power-up time 2 4.5 4.5 s 1 maximum sclk frequency is 50 mhz at v dd = 2.7 v to 5.5 v, 1.8 v v logic v dd . guaranteed by design and characterization; not production tested. 2 time to exit power-down to normal mode of ad5686r / ad5685r / AD5684R operation, 32 nd clock edge to 90% of dac midscale value, with output unloaded. figure 2. serial write operation t 4 t 3 sclk sync sdin t 1 t 2 t 5 t 6 t 7 t 8 db23 t 9 t 10 t 11 ldac 1 ldac 2 t 12 1 asynchronous ldac update mode. 2 synchronous ldac update mode. reset t 13 t 14 v out db0 10485-002
data sheet ad5686r/ad5685r/AD5684R rev. b | page 7 of 32 daisy-chain and readback timing characteristics all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 4 and figure 5. v dd = 2.7 v to 5.5 v, 1.8 v v logic 5.5 v; v ref = 2.5 v. all specifications t min to t max , unless otherwise noted. v dd = 2.7 v to 5.5 v. table 5. 1.8 v ? v logic < ? 2.7? v 2.7 v ? v logic ? 5.5? v parameter 1 symbol min max min max unit sclk cycle time t 1 66 40 ns sclk high time t 2 33 20 ns sclk low time t 3 33 20 ns sync to sclk falling edge t 4 33 20 ns data setup time t 5 5 5 ns data hold time t 6 5 5 ns sclk falling edge to sync rising edge t 7 15 10 ns minimum sync high time t 8 60 30 ns minimum sync high time t 9 60 30 ns sdo data valid from sclk rising edge t 10 36 25 ns sclk falling edge to sync rising edge t 11 5 15 10 ns sync rising edge to sclk rising edge t 12 5 15 10 ns 1 maximum sclk frequency is 25 mhz or 15 mhz at v dd = 2.7 v to 5.5 v, 1.8 v v logic v dd . guaranteed by design and characterization; not production tested. circuit and timing diagrams figure 3. load circuit for digital output (sdo) timing specifications figure 4. daisy-chain timing diagram 10485-003 200a i ol 200a i oh v oh (min) t o output pin c l 20pf t 4 t 5 t 6 t 8 sdo sdin sync sclk 48 24 db23 db0 db23 db0 db23 input word for dac n undefined input word for dac n + 1 input word for dac n db0 t 11 t 12 t 10 10485-004
ad5686r/ad5685r/AD5684R data sheet rev. b | page 8 of 32 figure 5. readback timing diagram 10485-005 sync t 8 t 6 sclk 24 1 24 1 t 9 t 4 t 2 t 7 t 3 t 1 db23 db0 db23 db0 sdin nop condition input word specifies register to be read t 5 db23 db0 db23 db0 sdo selected register data clocked out undefined t 10
data sheet ad5686r/ad5685r/AD5684R rev. b | page 9 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v v logic to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v logic + 0.3 v operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 125c 16-lead tssop, ja thermal impedance, 0 airflow (4-layer board) 112.6c/w 16-lead lfcsp, ja thermal impedance, 0 airflow (4-layer board) 70c/w reflow soldering peak temperature, pb free (j-std-020) 260c esd 1 4 kv ficdm 1.5 kv 1 human body model (hbm) classification. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5686r/ad5685r/AD5684R data sheet rev. b | page 10 of 32 pin configuration an d function descripti ons figure 6. 16 - lead lfcsp pin configuration figure 7. 16 - lead tssop pin configuration table 6 . pin function descriptions pin no. mnemonic description lfcsp tssop 1 3 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. 2 4 gnd ground reference point for all circuitry on the part. 3 5 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 6 v out c analog output voltage from dac c. the output amplifier has rail -to - rail op eration. 5 7 v out d analog output voltage from dac d. the output amplifier has rail -to - rail operation. 6 8 sdo serial data output. can be used to daisy - chain a number of ad5686r / ad5685r / AD5684R devices together or can be used for readback. the serial data is transferred on the rising edge of sclk and is valid on the falling edge of the clock. 7 9 ldac ldac can be operated in two modes, asynchronously and synchronously . pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs t o simultaneously update. this pin can also be tied permanently low . 8 10 gain span set pin. when this pin is tied to gnd , all four dac outputs have a span from 0 v to v ref . if this pin is tied to v logic , all four dac s output a span of 0 v to 2 v ref . 9 11 v logic digital power supply. voltage ranges from 1.8 v to 5.5 v. 10 12 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 50 mhz. 11 13 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, d ata is transferred in on the falling edges of the next 24 clocks . 12 14 s din serial data input. this device has a 24 - bit input shift register. data is clocked into the register on the falling edge of the serial clock input. 13 15 reset asynchronous reset input. the reset input i s falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac register are updated with zero scale or mid scale , depending on the state of the rstsel pin. 14 16 rstsel power - on reset pin. tying this pin to gnd powers up all four dacs to zero scale. tying this pin to v logic powers up all four dacs to midscale. 15 1 v ref reference voltage. the ad5686r / ad5685r / AD5684R have a common reference pin. when using the internal reference, this is the reference output pin. when using an external reference, this is the refere nce input pin. the default for this pin is as a reference output. 16 2 v out b analog output voltage from dac b. the output amplifier has rail -to - rail operation. 17 n/a epad exposed pad . the exposed pad must be tied to gnd. 12 11 10 1 3 4 sdin sync sclk 9 v logic v out a v dd 2 gnd v out c 6 sdo 5 v out d 7 ldac 8 gain 16 v out b 15 v ref 14 rstsel 13 reset ad5686r/ad5685r/AD5684R notes 1. the exposed pad must be tied to gnd. top view (not to scale) 10485-006 1 2 3 4 5 6 7 8 v out b v out a gnd v out d v out c v dd v ref sdo 16 15 14 13 12 11 10 9 reset sdin sync gain ldac v logic sclk rstsel top view (not to scale) ad5686r/ ad5685r/ AD5684R 10485-007
data sheet ad5686r/ad5685r/AD5684R rev. b | page 11 of 32 typical performance characteristi cs figure 8. internal reference voltage vs. temperature (grade b) figure 9. internal reference voltage vs. temperature (grade a) figure 10 . refer ence output temperature drift histogram figure 11 . reference long - term stability/drift figure 12 . internal reference noise spectral density v s. frequency figure 13 . internal reference noise , 0.1 hz to 10 hz ?40 ?20 0 20 40 60 80 100 120 v ref (v) temperature (c) device 1 device 2 device 3 device 4 device 5 10485-212 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 v dd = 5v ?40 ?20 0 20 40 60 80 120 100 v ref (v) temperature (c) device 1 device 2 device 3 device 4 device 5 10485-109 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 v dd = 5v 90 0 10 20 30 40 50 60 70 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 number of units temperature drift (ppm/c) 10485-250 v dd = 5v 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 0 hour 168 hours 500 hours 1000 hours 10485-251 v dd = 5.5v 1600 0 200 400 600 800 1000 1200 1400 10 100 1k 10k 100k 1m nsd (nv/ hz) frequency (mhz) 10485-111 v dd = 5v t a = 25c ch1 2v m1.0s a ch1 160mv 1 t 10485- 1 12 v dd = 5v t a = 25c
ad5686r/ad5685r/AD5684R data sheet rev. b | page 12 of 32 figure 14 . internal reference voltage vs. load current figure 15 . internal reference voltage vs. supply voltage figure 16 . ad5686r inl figure 17 . ad5685r inl figure 18 . AD5684R inl figure 19 . ad5686r dnl 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 ?0.005 ?0.003 ?0.001 0.001 0.003 0.005 v ref (v) i load (a) 10485- 1 13 v dd = 5v t a = 25c 2.5002 2.5000 2.4998 2.4996 2.4994 2.4992 2.4990 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v ref (v) v dd (v) d1 d3 d2 10485- 1 17 t a = 25c 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 10000 20000 30000 40000 50000 60000 inl (lsb) code 10485- 1 18 v dd = 5v t a = 25c internal reference = 2.5v 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 2500 5000 7500 10000 12500 15000 16348 inl (lsb) code 10485-119 v dd = 5v t a = 25c internal reference = 2.5v 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 625 1250 1875 2500 3125 3750 4096 inl (lsb) code 10485-120 v dd = 5v t a = 25c internal reference = 2.5v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 10000 20000 30000 40000 50000 60000 dnl (lsb) code 10485-121 v dd = 5v t a = 25c internal reference = 2.5v
data sheet ad5686r/ad5685r/AD5684R rev. b | page 13 of 32 figure 20 . ad5685r dnl figure 21 . AD5684R dnl figure 22 . inl error and dnl error vs. temperature figure 23 . inl error and dnl error vs. v ref figure 24 . inl error and dnl error vs. supply voltage figure 25 . gain error and full - scale error vs. temperature 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 2500 5000 7500 10000 12500 15000 16383 dnl (lsb) code 10485-122 v dd = 5v t a = 25c internal reference = 2.5v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 625 1250 1875 2500 3125 3750 4096 dnl (lsb) code 10485-123 v dd = 5v t a = 25c internal reference = 2.5v 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 110 60 10 error (lsb) temperature (c) inl dnl 10485-124 v dd = 5v t a = 25c internal reference = 2.5v 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 error (lsb) v ref (v) inl dnl 10485-125 v dd = 5v t a = 25c internal reference = 2.5v 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 2.7 5.2 4.7 4.2 3.7 3.2 error (lsb) supply voltage (v) inl dnl 10485-126 v dd = 5v t a = 25c internal reference = 2.5v 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temperature (c) gain error full-scale error 10485-127 v dd = 5v t a = 25c internal reference = 2.5v
ad5686r/ad5685r/AD5684R data sheet rev. b | page 14 of 32 figure 26 . zero - code error and offset error vs. temperature figure 27 . gain error and full - scale error vs. supply figure 28 . zero - code error and offset error vs. supply figure 29 . tue v s. temperature figure 30 . tue v s. supply, gain = 1 figure 31 . tue v s. code 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 ?20 0 20 40 60 80 100 120 error (mv) temperature (c) offset error zero-code error 10485-128 v dd = 5v t a = 25c internal reference = 2.5v 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 2.7 5.2 4.7 4.2 3.7 3.2 error (% of fsr) supply voltage (v) gain error full-scale error 10485-129 v dd = 5v t a = 25c internal reference = 2.5v 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 2.7 5.2 4.7 4.2 3.7 3.2 error (mv) supply voltage (v) zero-code error offset error 10485-130 v dd = 5v t a = 25c internal reference = 2.5v 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?40 ?20 0 20 40 60 80 100 120 total unadjusted error (% of fsr) temperature (c) 10485-131 v dd = 5v t a = 25c internal reference = 2.5v 0.10 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 2.7 5.2 4.7 4.2 3.7 3.2 total unadjusted error (% of fsr) supply voltage (v) 10485-132 v dd = 5v t a = 25c internal reference = 2.5v 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 ?0.06 ?0.07 ?0.08 ?0.09 ?0.10 0 10000 20000 30000 40000 50000 60000 65535 total unadjusted error (% of fsr) code 10485-133 v dd = 5v t a = 25c internal reference = 2.5v
data sheet ad5686r/ad5685r/AD5684R rev. b | page 15 of 32 figure 32 . i dd histogram with external reference, 5 v figure 33 . i dd histogram with internal reference, v refout = 2.5 v , gain = 2 figure 34 . headroom/footroom vs. load current figure 35 . source and sink capability at 5 v figure 36 . source and sink capability at 3 v figure 37 . supply current vs. temperature 25 20 15 10 5 0 540 560 580 600 620 640 hits i dd (v) 10485-135 v dd = 5v t a = 25c external reference = 2.5v 30 25 20 15 10 5 0 1000 1020 1040 1060 1080 1100 1120 1140 hits i dd fullscale (v) 10485-136 v dd = 5v t a = 25c internal reference = 2.5v 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 5 10 15 20 25 30 v out (v) load current (ma) 10485-200 sourcing 2.7v sourcing 5v sinking 2.7v sinking 5v 7 ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x8000 0xc000 0x0000 10485-138 v dd = 5v t a = 25c gain = 2 internal reference = 2.5v 5 ?2 ?1 0 1 2 3 4 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x8000 0xc000 0x0000 10485-139 v dd = 3v t a = 25c external reference = 2.5v gain = 1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?40 110 60 10 current (ma) temperature (c) full-scale zero code external reference, full-scale 10485-140
ad5686r/ad5685r/AD5684R data sheet rev. b | page 16 of 32 figure 38 . settling time, 5.25 v figure 39 . power - on reset to 0 v figure 40 . exiting power - down to midscale figure 41 . digital - to- analog glitch impulse figure 42 . analog crosstalk, channel a figure 43 . 0.1 hz to 10 hz output noise plot, external reference 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 10 320 160 40 80 20 v out (v) time (s) dac a dac b dac c dac d 10485-141 v dd = 5v t a = 25c internal reference = 2.5v ? to ? scale ?0.01 0 0.06 0.01 0.02 0.03 0.04 0.05 ?1 0 6 1 2 3 4 5 ?10 15 10 0 5 ?5 v out (v) v dd (v) time (s) ch d v dd ch a ch b ch c 10485-142 t a = 25c internal reference = 2.5v 0 1 3 2 ?5 10 0 5 v out (v) time (s) ch d sync ch a ch b ch c 10485-143 v dd = 5v t a = 25c internal reference = 2.5v gain = 1 gain = 2 2.4988 2.5008 2.5003 2.4998 2.4993 0 12 8 10 4 6 2 v out (v) time (s) 10485-144 channel b t a = 25c v dd = 5.25v internal reference code = 7fff to 8000 energy = 0.227206nv-sec ?0.002 ?0.001 0 0.001 0.002 0.003 0 25 20 10 15 5 v out ac-coupled (v) time (s) ch b ch c ch d 10485-145 ch1 10v m1.0s a ch1 802mv 1 t 10485-146 v dd = 5v t a = 25c external reference = 2.5v
data sheet ad5686r/ad5685r/AD5684R rev. b | page 17 of 32 figure 44 . 0.1 hz to 10 hz output noise plot, 2.5 v internal reference figure 45 . noise spectral density figure 46 . total harmonic distortion @ 1 k hz figure 47 . settling time vs. capacitive load figure 48 . multiplying bandwidth, ext ernal ref erence = 2.5 v , 0.1 v p - p , 10 k hz to 10 mhz ch1 10v m1.0s a ch1 802mv 1 t 10485-147 v dd = 5v t a = 25c internal reference = 2.5v 0 200 400 600 800 1000 1200 1400 1600 10 1m 100k 1k 10k 100 nsd (nv/ hz) frequency (hz) full-scale midscale zero-scale 10485-148 v dd = 5v t a = 25c internal reference = 2.5v ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 20000 16000 8000 12000 4000 2000 18000 10000 14000 6000 thd (dbv) frequency (hz) 10485-149 v dd = 5v t a = 25c internal reference = 2.5v 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 1.590 1.630 1.620 1.600 1.610 1.625 1.605 1.615 1.595 v out (v) time (ms) 0nf 0.1nf 10nf 0.22nf 4.7nf 10485-150 v dd = 5v t a = 25c internal reference = 2.5v ?60 ?50 ?40 ?30 ?20 ?10 0 10k 10m 1m 100k bandwidth (db) frequency (hz) 10485-151 v dd = 5v t a = 25c external reference = 2.5v, 0.1v p-p
ad5686r/ad5685r/AD5684R data sheet rev. b | page 18 of 32 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot is shown in figu re 16. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differe ntial nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 19. zero - cod e error zero - code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the ad5686r becau se the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the output amplifier. zero - code error is expressed in mv. a plot of zero - code error vs. temperature can be seen in figure 26. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed in percent of full - scale range (% of fsr) . a plot of full - scale error vs. temperature can be seen in figure 25. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. offset error drift this is a measurement of the change in offset error with a change in temperature. it is expre ssed in v/c. gain temperature coefficient this is a measurement of the change in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5686r with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in mv/v . v ref is held at 2 v, and v dd is varied by 10 %. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input ch ange and is measured from the rising edge of sync . digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s ec , and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) (see figure 41). digital feedthrough digital feedthrou gh is a measure of the impulse injected into the analog out put of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv - s ec , and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. noise spectral density this is a measurement of the internally generate d random noise. random noise is characterized as a spectral density (nv/hz). it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density is shown in fig ure 45. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standal one mode and is expressed in nv - s ec .
data sheet ad5686r/ad5685r/AD5684R rev. b | page 19 of 32 analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then execute a software ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv - s ec . dac -to - dac crosstalk this is the glitch impulse transferred to the output of one d ac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa) , using the write to and update command s while monitor - ing the o utput of the victim channel that is at midscale. the energy of the glitch is expressed in nv - s ec . multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (wit h full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db. voltage reference tc voltage r eference tc is a measure of the change in the reference output voltage with a change in temperature. the reference tc is calculated using the box method, which defines the tc as the maximum change in the reference output over a given tempera - t ure range expressed in ppm/c , as follows; 6 10 ? ? ? ? ? ? ? ? ? = temprange v v v tc refnom refmin refmax where: v refmax is the maximum reference output measured over the total temperature range. v refmin is the minimum reference output measured over the total temperature range. v refnom is the no m inal reference output voltage, 2.5 v. temprange is the specified temperature range of ? 40c to +10 5c.
ad5686r/ad5685r/AD5684R data sheet rev. b | page 20 of 32 theory of operation digital - to - analog converter t he ad5686r / ad5685r / AD5684R are quad 1 6 - /14 - /12 - bit, serial input, voltage output dacs with an internal reference. the parts operate from supply voltages of 2.7 v to 5.5 v. data is written to the ad5686r / ad5685r / AD5684R in a 2 4 - bit word forma t via a 3 - wire serial interface. th e ad5686r / ad5685r / AD5684R incorporate a power - on reset circuit to ensure that the dac output powers up to a known output state. the devices also have a software power - down mode that reduces the typical current consumption to typically 4 a . transfer function the internal reference is on by default. to use an external reference , only a nonreference option is available. because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n ref out d gain v v 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register as follows: 0 to 4,095 for the 12 - bit device . 0 to 16,383 for the 14 - bit device. 0 to 65,535 for the 16 - bit device . n is the dac resolution. gain is the gain of the output amplifier and is set to 1 by default. this can be set to 1 or 2 using the g ain select pin . when this pin is tied to gnd, all four dac outputs have a span from 0 v to v ref . if this pin is tied to v dd , all four dac s output a span of 0 v to 2 v ref . dac architecture the dac architect ure consists of a string dac followed by an output amplifier. figure 49 shows a block diagram of the dac arc hitecture. figure 49 . single dac channel architecture block diagram the resistor string structure is shown in figure 50 . it is a string of resistors, each of value r. the code loaded to the dac regis ter determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guar anteed monotonic. figure 50 . resistor string structure internal reference the ad5686r / ad5685r / AD5684R on - chip reference is on at power - up but can be disabled via a write to a control register. see the i nternal reference setup section for details. the ad5686r / ad5685r / AD5684R ha ve a 2.5 v, 2 ppm/c reference , giving a full - scale outpu t of 2.5 v or 5 v , depending on the state of the gain pin. the internal reference associated with the device is available at the v ref pin. this buffe r ed reference is capable of driving external loads of up to 10 ma . output amplifier s the output buffer amplifier can generate rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the actual range depends on the value of v ref , the gain pin, offset error , and gain error. the gain pin selects the gain of the output . ? if this pin is tied to gnd , all four output s have a gain of 1 and the output range is 0 v to v ref . ? if this pin is tied to v logic , all four output s have a gain of 2 and the output range is 0 v to 2 v ref . the se amplifier s are capable of driving a load of 1 k? in parallel with 2 n f to gnd. the slew rate is 0.8 v/s with a ? to ? scale settling time of 5 s. 10485-052 input register 2.5v ref dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 10485-053 r r r r r to output amplifier v ref
data sheet ad5686r/ad5685r/AD5684R rev. b | page 21 of 32 serial interface t he ad5686r / ad5685r / AD5684R have a 3 - wire serial interface ( sync , sclk, and s din) that is compatible with spi, qspi, and microwire interface stan dards as well as most dsps. see fig ure 2 for a timing diagram of a typi cal write sequence. the ad5686r / ad5685r / AD5684R contain an sdo pin to allow the user to daisy - chain multiple devices together (see the daisy - chain operation section) or for readback . input shift register the input shift register of the ad5686r / ad5685r / AD5684R is 2 4 bits wide. data is loaded msb first (db2 3 ) and t he first four bits are the com mand bits, c3 to c0 (see table 7 ), followed by the 4 - bit dac address bits, dac a, dac b, dac c, dac d (see table 8 ), and finally the bit data - word. the data - word comprises 1 6 - bit, 14 - bit, or 1 2 - bit input code, followed by zero, two or four dont care bits for the ad5686r , ad5685r , and AD5684R , respectively (see figure 51, figure 52, and figure 53 ). these data bits are transfe rr ed to the input register on the 24 falling edges of sclk and are updated on the rising edge of sync . comm ands can be executed on individual dac channels, combined dac channels , or on all dacs , depending on the address bits selected . table 7 . command definitions command c3 c2 c1 c0 description 0 0 0 0 no operation 0 0 0 1 write to input register n (d ependent on ldac ) 0 0 1 0 update dac register n with contents of input register n 0 0 1 1 wr ite to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software r eset (power - on reset) 0 1 1 1 internal r eference setup register 1 0 0 0 set up dcen register (daisy - chain enable) 1 0 0 1 set up r eadback register (readback enable) 1 0 1 0 reserved reserved 1 1 1 1 reserved table 8 . address commands address (n) selected dac channel 1 dac d dac c dac b dac a 0 0 0 1 dac a 0 0 1 0 dac b 0 1 0 0 dac c 1 0 0 0 dac d 0 0 1 1 dac a and dac b 1 1 1 1 all dacs 1 any combination of dac channels can be selected using the address bits. figure 51 . ad5686r input shift register content figure 52 . ad5685r input shift register content figure 53 . AD5684R input shift register content address bits command bits dac d dac c dac b dac a d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 db23 (msb) db0 (lsb) data bits 10485-054 address bits command bits dac d dac c dac b dac a d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x c3 c2 c1 c0 db23 (msb) db0 (lsb) data bits 10485-055 address bits command bits dac d dac c dac b dac a d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x c3 c2 c1 c0 db23 (msb) db0 (lsb) data bits 10485-056
ad5686r/ad5685r/AD5684R data sheet rev. b | page 22 of 32 standalone operation the write sequence begins by bringing the s ync line low. data from the s din line is clocked into the 24 - bit input shift regis ter on the falling edge of sclk . after the last of 24 data bit s is clocked in , sync s hould be brough t high . the programmed function is then executed, that is, an ldac - dependent change in dac register contents and/or a change in the mode of operation. if sync is taken high at a c lock before the 2 4 th clock, it is considered a valid frame and invalid data may be loaded to the dac. sync must be b rought high for a minimum of 20 n s (single channel, see t 8 in figure 2 ) before the next write sequence so that a falling edge of sync can initiate the next write sequence. sync should be idled at rails between write sequences for even lower power operation of the part. t he sync line is kept low for 2 4 falling edges of sclk, and the dac is updated on the rising edge of sync . when the data has been transferred into the input register of the ad dressed dac, all dac registers and outputs can be updated by taking ldac low while the sync line is high. write and update com mands write to input register n (dependent on ldac ) command 0001 allows the user to write to each dac s dedicated input register individually. when ldac is low , the input register is transparent (if not controlled by the ldac mask register). update dac register n with contents of input regist er n command 0010 loads the dac registers/outputs with the contents of the input registers selected and update s the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 allows the user to write to the dac registers and update the dac outputs directly.
data sheet ad5686r/ad5685r/AD5684R rev. b | page 23 of 32 daisy - chain operation for systems that contain several dacs , the sdo pin can be used to daisy - chain several devices toge ther and is enabled through a software executable daisy - chain ena bl e (dcen) command. command 1000 is reserved for this dcen function (see table 7 ). the daisy - chain mod e is enabled by setting bit db 0 in the dcen register. the default setting is standalone mode, where db0 = 0 . table 9 shows how the state of the bit corresponds to the mode of operation of the device. table 9 . daisy - chain enable ( dcen ) register db0 description 0 standalone mode (default) 1 dcen mode figure 54 . daisy - chaining the ad5686r / ad5685r / AD5684R the sclk pin is continuously applied to the input shift register when sync is low. if more than 2 4 clock pulses are applied, the data ripples out of the input shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the s din input on the next dac in the chain, a daisy - chain interface is constructed. ea ch dac in th e system requires 24 clock pulses. t herefore, the total numb er of clock cycles must equal 24 n, where n is the total number of devices that are updated. if sync is taken high at a c lock that is not a multiple of 2 4 , it is considere d a valid frame and invalid data may be loaded to the dac . when the serial transfer to all devices is complete, sync is taken high . this latches the input data in each device in the daisy chain and prevents any further data from bein g clocked into the input shift register . the serial clock can be continuous or a gated clock. a continuous sclk source can be used only if sync can be held low for the correct number of clock cycles. in gated clock mode, a burst cloc k containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. readback operation readback mode is invoked through a software executable readback command. i f the sdo output is disabled via the d aisy - chain mode disable bit in the control register, it is automatically enabled for the duration of the read operation, after which it is disabled again. command 100 1 is reserved for the readback function. this command , in asso ciation with selecting one of address bits , dac a to dac d , select s the register to read. note that only one dac register can be selected during readback. the remaining three address bits must be set to logic 0 . the remaining data bits in the writ e sequenc e are dont care bits. if more than one or no bits are selected , dac channel a is read back by default. during the next spi write, the data appearing on the sdo output contains the data from the previously addressed register. for example, to read back the dac register for channel a, the following sequence should be implemented: 1. write 0x90 0000 to the ad5686r / ad5685r / ad5684 r input register. this configures the part for read mode with the dac register of channel a selected. note that all data bits , db15 to db0 , are dont care bits. 2. follow this with a se cond write, a nop condition, 0x0 00000. during this write, the data from the register is clocked out on the sdo line . db23 to db20 contain undefined data , and the last 16 bits contain the db19 to db4 dac register contents. 68hc11* miso sdin sclk mosi sck pc7 pc6 sdo sclk sdo sclk sdo sdin sdin sync sync sync ldac ldac ldac ad5686r/ ad5685r/ AD5684R ad5686r/ ad5685r/ AD5684R ad5686r/ ad5685r/ AD5684R *additional pins omitted for clarity. 10485-057
ad5686r/ad5685r/AD5684R data sheet rev. b | page 24 of 32 power - down operation t he ad5686r / ad5685r / AD5684R contain three separate power - down mode s. command 0100 is designated for the power - down function (see table 7 ). these power - down modes are software - programmable by setting eight bits, bit db7 to bit db0 , in the input shift register. there are two bits associated with each dac channel. table 10 shows how the state of the two bits corresponds to the mode of operation of the device. table 10 . modes of operation operating mode pdx1 pdx0 normal operation 0 0 power - down modes 1 k ? to gnd 0 1 100 k ? to gnd 1 0 three - state 1 1 any or all dacs (dac a to dac d ) can be powered down to the selected mode by setting th e corresponding bits . see table 11 for the contents of the input shift register during the power - down/power - up operation. when both bit pd x 1 and bit pd x 0 (where x is the channel selected) in the input shift register are set to 0, the part s work normally with its normal power consumption of 4 ma at 5 v. however, for th e three power - down modes, the supply current falls to 4 a at 5 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values . this has the advantage that the output impedance of the part is known while the part is in power - down mode. there are three different power - dow n options. the output is connected inter nally to gnd through either a 1 k? or a 100 k? resistor, or it is left open - circuited (three - state). the output stage is illustrated in figure 55. figure 55 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power - down mode is activated. however, the contents of the dac register are unaffected when in power - down. the dac register can be updated while the device is in power - down mode. the time required to exit power - down is typically 4.5 s for v dd = 5 v . to reduce the current consumption further , the on - chip reference can be powered off. see the i nternal reference setup section. table 11 . 24- bit input shift register contents of power - down/power - up operation 1 db23 db2 2 db2 1 db20 db19 to db16 db15 to db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) 0 1 0 0 x x pdd1 pdd0 pdc1 pdc0 pdb1 pdb0 pda1 pda0 command bits (c3 to c0) address bits dont care power - down select dac d power - down select dac c power - down select dac b power - down select dac a 1 x = dont care. resistor network v out x dac power-down circuitry amplifier 10485-058
data sheet ad5686r/ad5685r/AD5684R rev. b | page 25 of 32 load dac ( hardware ldac p in ) the ad5686r / ad5685r / AD5684R dacs have double buffered interfaces consisting of two banks of registers: inp ut registers and dac registers. the user can write to any combination of the input registers. updates to the dac register are controlled by the ldac pin. figure 56 . simplified diagram of input loading circuitry for a single dac instantaneous dac updating ( ldac held low ) ldac is held low while data is clocked into the inpu t register using command 0001 . both t he addressed input register and the dac register are updated on the rising edge of sync and the output begins to change (see table 13) . deferred dac updating ( ldac is pulsed low ) ldac is held high while data is clocked into the input register using command 0001 . all dac outputs are asynchronously updated by taking ldac low after sync has been taken high. the update now occurs on the falling edge of ldac . ldac mask register command 0101 is reserved for this software ldac function. address bits are ignored. writi ng to the dac , using command 0101, loads the 4 - bit ldac register (db3 to db0). the default for each channel is 0; that is, the ld ac pin works normally. setting the bits to 1 forces this dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin . this flexibility is use ful in applications where the user wishes to select which channels respond to the ldac pin . table 12. ldac overwrite definition load ldac register ldac bits (db3 to db0) ldac pin ldac operation 0 1 or 0 determined by the ldac pin. 1 x 1 dac channels update and override the ldac pin. dac channels see ldac as 1 . 1 x = dont care. the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 12 ). setting the ldac bits (db0 to db3 ) to 0 for a dac channel means that this channels update is controlled by the hardware ldac pin. table 13. write commands and ldac pin truth table 1 commands description hardware ldac pin state input register contents dac register contents 0001 write to input register n ( d ependent on ldac ) v logic data u pdate no change (no update) gnd 2 data u pdate data u pdate 0010 update dac register n with contents of input register n v logic no c hange updated with i nput register contents gnd no c hange updated with i nput register contents 0011 write to and update dac channel n v logic data u pdate data u pdate gnd data u pdate data u pdate 1 a high to low hardware ldac pin transition always updates the contents of the contents of the dac register with the contents of the input register on cha nnels that are not masked (blocked) by the ld ac mask register. 2 when ldac is permanently tied low, the ldac mask bits are ignored. sync sclk v out x dac register interface logic output amplifier ldac sdo sdin v ref input register 16-/14-/12-bit dac 10485-059
ad5686r/ad5685r/AD5684R data sheet rev. b | page 2 6 of 32 hardware reset ( reset ) reset is an active low reset that allows the outputs to be cleared to either zero scale or midscale . the clear code value is user selectable via the reset sel ect pin . it is necessary to keep reset low for a minimum amount of time to complete the operation (see figure 2 ) . when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. the outputs cannot be updated with a new value while the reset pin is low. there is also a software executable reset function that resets the dac to the p ower - on reset code. command 0 110 is designated for this software reset function (see table 7 ). any events on ldac or reset during power - on reset are ignored . reset select p in (rstsel) th e ad5686r / ad5685r / AD5684R contain a power - on reset circuit that controls the output voltage durin g power - up. by connecting the r stsel pin low, th e output powers up to zero scale. note that this is outside the linear region of the dac; by connecting the rstsel pin high, v out powers up to m idscale. the output remains powered up at this level until a valid write sequence is made to the dac. i nternal reference se tup the on - chip reference is on at power - up by default. to reduce the supply current , t his reference can be turned off by setting so ftware programmable bit, db0, in the control register. table 14 shows how the state of the bit corresponds to t he mode of operation. command 0111 is reserved for setting up the internal reference (see figure 9 ). table 14 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device during internal reference setup. table 14 . reference set up register internal reference setup register (db0) action 0 reference on (default) 1 reference off solder heat reflow as with all ic reference voltage circuits, the reference value experience s a shift induced by the soldering process. a nalog d evices, i nc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. the output voltage spec ification quoted previously includes the eff ect of this reliability test. figure 57 shows the effect of solde r heat reflow (shr) as measured through the reliability test (precondition). figure 57 . shr reference voltage shift l ong - term temperature d rift figure 58 shows the change in v ref value after 1000 h ou rs in life test at 150 c . figure 58 . reference drift through to 1000 hou rs 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 10485-060 postsolder heat reflow presolder heat reflow 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 0 hour 168 hours 500 hours 1000 hours 10485-061
data sheet ad5686r/ad5685r/AD5684R rev. b | page 27 of 32 thermal hysteresis thermal h ysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold , to hot , and then back to ambient. thermal h ysteresis data is shown in figure 59 . it is measured by sweeping the temperature from ambient to ? 40 c, then to + 105 c , and returning to ambient. the v ref delt a is then measured between the two ambient measurements and shown in blue in figure 59 . the same temperature sweep and measurements were immediately repeated and the results are shown in red in figure 59. figure 59 . thermal hysteresis table 15 . 24- bit input s hift register contents for internal reference setup command 1 db23 (msb) db2 2 db2 1 db20 db19 db18 db17 db16 db15 to db 1 db0 (lsb) 0 1 1 1 x x x x x 1/0 command bits (c3 to c0) address bits (a2 to a0) dont care reference setup register 1 x = dont care. 9 8 7 6 5 4 3 2 1 0 50 0 ?50 ?100 ?150 ?200 hits distortion (ppm) 10485-062 first temperature sweep subsequent temperature sweeps
ad5686r/ad5685r/AD5684R data sheet rev. b | page 28 of 32 applications information microprocessor inter facing microproc essor interfacing to the ad5686r / ad5685r / AD5684R is via a serial bus that uses a standard protocol that is compatible with dsp proces sors and microcontrollers. the communications channel req uires a 3 - or 4 - wire interface consisting of a clock signal, a data signal, and a sy n chronization signal. the devices require a 2 4 - bit data - word with data valid on the rising edge of sync . ad5686r / ad5685r / AD5684R to adsp - bf531 interface the spi interface of the ad5686r / ad5685r / a d5684r is designed to be easily connected to industry - standard dsps and microcontrollers. figure 60 shows the ad5686r / ad5685r / AD5684R connect ed to the analog devices blackfin? dsp. the blackfin has an integrated spi port that can be connected directly to the spi pins of the ad5686r / ad5685r / AD5684R . figure 60 . adsp - bf531 interface ad5686r / ad5685r / AD5684R to sport interface the analog devices adsp - bf527 has one sport serial port. figure 61 shows how one sport interface can be used to control the ad5686r / ad5685r / AD5684R . figure 61 . sport interface layout guidelines in any circuit where accuracy is important, careful consider - ation of the power supply and ground return layout helps to ensure the rated performance. the pcb on which the ad5686r / ad5685r / AD5684R are mounted should be designed so that th e ad5686r / ad5685r / AD5684R lie on the analog plane. the ad5686r / ad5685r / AD5684R should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply , located as close to the package as possible, ideally right up against t he device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at h igh frequencies to handle transient currents due to internal logic switching. in systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the ad5686r / ad5685r / AD5684R have an exposed paddle beneath the device. connect this paddle to the gnd supply for the part. f or optimum performance, use special considerations to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, solder the exposed paddle on the bottom of the package to the corresponding thermal land p addle on the pcb. design thermal vias into the pcb land paddle area to further improve heat dissipation. the gnd plane on the device can b e increased (as shown in figure 62 ) to provide a natural heat sinking effect. figure 62 . paddle connection to board adsp-bf531 sync spiselx sclk sck sdin mosi ldac pf9 reset pf8 ad5686r/ ad5685r/ AD5684R 10485-164 adsp-bf527 sync sport_tfs sclk sport_tsck sdin sport_dto ldac gpio0 reset gpio1 ad5686r/ ad5685r/ AD5684R 10485-165 ad5686r/ ad5685r/ AD5684R gnd plane board 10485-166
data sheet ad5686r/ad5685r/AD5684R rev. b | page 29 of 32 galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. i coupler? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loading struc- ture of the ad5686r / ad5685r / AD5684R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 63 shows a 4-channel isolated interface to the ad5686r / ad5685r / AD5684R using an adum1400 . for further information, visit http://www.analog.com/icoupler . figure 63. isolated interface encode serial clock in controller adum1400 1 serial data out sync out load dac out decode to sclk to sdin to sync to ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 1 additional pins omitted for clarity. 10485-167
ad5686r/ad5685r/AD5684R data sheet rev. b | page 30 of 32 outline dimensions figure 64. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-22) dimensions shown in millimeters figure 65. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab
data sheet ad5686r/ad5685r/AD5684R rev. b | page 31 of 32 ordering guide model 1 resolution temperature range accuracy reference t empco (ppm/ c) package description package option branding ad5686racpz -rl7 16 bits ? 40c to +105c 8 lsb inl 5 (typ) 16 - lead lfcsp_w q cp -1 6 -2 2 djm ad5686rbcpz - rl7 16 bits ? 40c to +105c 2 lsb inl 5 (max) 16 - lead lfcsp_w q cp -16 -22 djn ad5686raruz 16 bits ? 40c to +105c 8 lsb inl 5 (typ) 16 - lead tssop ru -1 6 ad5686raruz -rl7 16 bits ? 40c to +105c 8 lsb inl 5 (typ) 16 - lead tssop ru -1 6 ad5686rbruz 16 bits ? 40c to +105c 2 lsb inl 5 (max) 16 - lead tssop ru -16 ad5686rbruz -rl7 16 bits ? 40c to +105c 2 lsb inl 5 (max) 1 6 - lead tssop ru -1 6 ad5685rbcpz - rl7 14 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead lfcsp_w q cp -16 -22 djk ad5685raruz 14 bits ? 40c to +105c 4 lsb inl 5 (typ) 16 - lead tssop ru -1 6 ad5685raruz -rl7 14 bits ? 40c to +105c 4 lsb inl 5 (typ) 16 - lead tssop ru -1 6 ad5685rbruz 14 bits ? 40c to +105c 1 lsb inl 5 (max) 1 6 - lead tssop ru -1 6 ad5685rbruz -rl7 14 bits ? 40c to +105c 1 lsb inl 5 (max) 1 6 - lead tssop ru -1 6 AD5684Rbcpz - rl7 12 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead lfcsp_w q cp -16 -22 djg AD5684Raruz 12 bits ? 40c to +105c 2 lsb inl 5 (typ) 16 - lead tssop ru -1 6 AD5684Raruz - rl7 12 bits ? 40c to +105c 2 lsb inl 5 (typ) 16 - lead tssop ru - 1 6 AD5684R b ruz 12 bits ? 40c to +105c 1 lsb inl 5 (max) 1 6 - lead tssop ru - 1 6 AD5684R b ruz -rl7 12 bits ? 40c to +105c 1 lsb inl 5 (max) 1 6 - lead tssop ru -1 6 eval - ad5686rsdz ad 5686 r tssop evaluation board eval - AD5684Rsdz ad 5684 r tssop evaluation board 1 z = rohs compliant part.
ad5686r/ad5685r/AD5684R data sheet rev. b | page 32 of 32 notes ?2012C2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10485-0-6/13(b)

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